Wafer-level 3D integration technology
نویسندگان
چکیده
integration technology S. J. Koester A. M. Young R. R. Yu S. Purushothaman K.-N. Chen D. C. La Tulipe, Jr. N. Rana L. Shi M. R. Wordeman E. J. Sprogis An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.
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عنوان ژورنال:
- IBM Journal of Research and Development
دوره 52 شماره
صفحات -
تاریخ انتشار 2008